1. This solution find obscure bugs, increasing design confidence through exhaustive analysis, before simulation test environments are available, and also boost productivity and functional verification quality by targeting verification tasks that are difficult to complete.
Version 2021.x releases have significant enhancements and changes compared with the 2020.x series of releases.
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- new directive to change the promotion attributes of specified CDC constraint.
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- new directive to set preferences for isolation strats.
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- asynchronous set or reset signal is connected to data pin.
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- case statement has fewer case items.
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- comment density of a design file is less than the specified limit.
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- function argument is a constrained array.
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- multiple sequential blocks use the same clock.
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- net is declared and assigned in the same statement
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- use of the specified package is not allowed.
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- package name does not follow standard naming rules.
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- use of the specified pragma is not allowed.
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- register is assigned a reset value, which is not allowed.
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- synchronous control signal is internally generated.
The following table list the customer defects fixed and enhancements requested in the 2021.1 release.
a part of Siemens Digital Industries Software, continues to evolve in response to the growing complexity of SoC designs. Besides the sheer size of designs, the inclusion of multiple embedded processors and advanced interconnect systems, increasing software content and the configurability required by multi-platform based designs require a functional verification solution that unifies a broad arsenal of verification solutions.
Questa lets you apply CDC verification, formal verification, mixed-signal verification, portable stimulus, and other powerful technologies to maximize the effectiveness of your verification at the block- and subsystem-level so your system-level verification can focus on system-level functionality, including software, without having to worry about lower-level bugs taking away from your productivity. No one wants to compromise product quality. However, -to market pressures dominate SoC projects. To deliver quality within schedule requires improving the to achieve coverage and quality goals and improving debug productivity.
statically analyze a design's behavior with respect to a given set of properties; then exhaustively explore all possible input sequences in a breadth-first search manner. This uncovers design errors that would otherwise be missed or are impractical to find with simulation-based methods.
Questa Formal Apps boost verification efficiency and design quality by exhaustively addressing verification tasks that are difficult to complete with traditional methods, and they don't require formal or assertion-based verification experience.
Properties are synthesized from a combination of automatic RTL design analysis and a high-level specification of design intent. The generated properties are then exhaustively verified with formal analysis ees.
The Questa Formal App suite includes applications to address tasks such as: static and conditional connectivity checking, secure path integrity checking, unreachable code identification, X-state propagation, state-space analysis, and register verification. Additionally, the Questa Sequential Logic Equivalence Checking (SLEC) App uses formal methods to perform exhaustive comparisons between inputs to reveal any behavioral discrepancies that could arise in clock gating, ECO integration, re-pipelining, or fault mitigation logic.
is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world's most successful electronic, sonductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Mentor Questa Formal
2021.1
x64 english
PC *
1.4 Gb



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