What you'll learn
VHDL Programming Synthesis & Simulation Xilinx FPGA & CPLD Devices Xilinx ISE Design Suite & Implementation
Requirements
Digitial Logic Design Concepts Basic knowledge of any Programming Language ( Like Ex. C Programming )
Description
Description : Contents of this PCB Design Course are developed using a VHDL language for Xilinx ISE Design Suite , Design Software , for Xilinx based FPGAs & CPLDs devices . This Tool supports to Windows & Linux Platforms . The VHDL Programs runs on all Editions of Xilinx ISE Design Suite , including Xilinx ISE Webpack Edition , which is a Free Download Edition after completing successful Registration procedure with Xilinx ( On Xilinx Website ) .
Course Learning Duration - You can Learn VHDL Programming within 2 (Two ) Days , provided you have prior knowledge of Digital Electronics Fundamentals of Combinational & Sequential Logic Design & any basic level knowledge of Programming language like C Programming .
Video Content of VHDL Programs is explained in a Step by Step manner ( Like VHDL Source Code , VHDL Synthesis ( RTL & Technology Schematic ) , Test Bench & Behavioral Simulation ) and with Short Video sessions in a simple way for better understanding , even for the Beginners .
This Course is mainly designed for Beginners / Polytechnic & Engineering Students / University Students / Hobbyists .
In this course you will learn about --
About IC Technology
Digital Logic Design Concepts
Digital Logic Families
VHDL Language Basics - Reserve Words ( Keywords ) , Identifiers , Operators , DataTypes , Data Objects .
VHDL Structure - Entity , Architecture , Library, Package .
VHDL Process .
VHDL - Sequential & Concurrent Statements .
Target Device Selection ( FPGA or CPLD )
VHDL Program ( Design / Source Code )
VHDL Test bench ( Source Code )
Simulation Using ISim
Synthesis ( RTL & Technology Schematic )
Applying Constraints ( Pin Locking Constraints & Timing Constraints )
Design Implementation ( Post Route Timing Simulation ) ( Static Timing )
VHDL Programming Examples :
- Logic Gates
- MUX (Multiplexers )
- Decoder
- Encoder
- Half Adder & Full Adder
- VHDL Behavioral Modeling Example
- VHDL Data Flow Modeling Example
- VHDL Structural Modeling Example
- D Latch
- D Flip-Flop
- D Flip-Flop ( with Synchronous Reset & with Asynchronous Reset )
- FSM - Finite state Machine using VHDL
- Counters ( Binary Up Counter , Binary Down Counter & Binary Up-Down Counter )
- Shift Registers ( SISO, SIPO , PISO & PIPO Type )
- ALU - Arithmetic & Logic Unit
- Memory Unit - RAM
- Memory Unit - ROM
- VHDL Project Integration
Instructor has more than a 22 Years of Design / Training Experience after M.Tech. in Electronics Design & Technology , which includes the Experience in Electronic Circuit Design , Embedded System , VLSI - VHDL & Verilog Programming for Xilinx FPGAs , CPLDs using Xilinx ISE Tool / Xilinx Vivado Tool , PSOC1 using Cypress PSOC Designer & PSOC3 /PSOC4 using Cypress PSOC Creator , Microcontroller Programming for MCS-51 (8051 ) family using Keil uVision 4 , Programming ATMega 16/32/128 using Atmel AVR Studio , Programming Microchip PIC 16/18 using MPLAB , Arduino Programming for Arduino Uno , MSP430 of Texas Instruments with Energia , Raspberry Pi & Raspbian Linux , Python Programming with Python 3.8 ( IDLE) , Python Thonny , Python Pycharm , Anaconda Navigator - Jupyter Notebook , Spyder Python , Google Colab , Crouzet Millenium 3 for PLC Programming & also PCB design which includes PCB Softwares such as EasyEDA , KiCad 5.1 , Fritzing & Express PCB .
Who this course is for:
Beginners , Hobbyists , Teachers & anyone who is interested to Learn to Create Digital Logic Designs , using FPGA / CPLD . University Students , Students from Engineering colleges & Polytechnic Institutes , who want to create the Design for their Programmable Electronics based Academic Project . Anyone who wants to make career in FPGA , VHDL Programming . Electronic Designers / Embedded Engineers / Electronic Circuit Design Professionals , who are new to VHDL Programming & FPGA / CPLD Device Architectures .

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